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Altera_Forum
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11 years ago

Transceiver PCS Question

When implementing GIGE on CycloneV transceiver using Custom Phy is needed to perform "running disparity rules" on FPGA logic outside transceiver phy? I think the answer is yes, but I would to c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes, correct. If I test the phy, I monitor rx_runningdisp and rx_errdetect status signals too. Because the running disparity of K28.5 in IDLE code (/I/) must be minus disparity (rx_runningdisp = 1).

The simple test pattern will be /I/I/I/I/I/I/I/I/S/8'hAA/T/R/R/I/I/I/I/I/I/I/I. rx_disperr and rx_errdetect should be low, and rx_runningdisp should be high when rx_paralleldata = 8'hBC, tx_datak = 1'b1.