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Altera_Forum
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11 years ago

Transceiver PCS Question

When implementing GIGE on CycloneV transceiver using Custom Phy is needed to perform "running disparity rules" on FPGA logic outside transceiver phy? I think the answer is yes, but I would to c...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Yes. If you transmit even length packet, the FCS must be followed by /T/R/ (tx_paralleldata = 16'hFDF7, tx_datak = 2'b11). If you transmit odd length frames, the FCS must be followed by /T/R/R/ (tx_paralleldata = 24'hFDF7F7, tx_datak = 3'b111).

BTW, the GIGE mode is tricky. You should go through AN537 if you plan to use 1000BASE-X/SGMII Auto-Negotiation.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an537.pdf