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Honored Contributor
Honored ContributorTip/suppornt on debugging a VHDL project on Altera
Hi
I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation in which two signals are touched within an 'if' block. In simulation everything is doing fine, but when I got it programmed and running on FPGA, only one of them is touched. The piece of VHDL code is the following: flash_process(clk) begin if(rst='1') then ............ int_flash_en <= '0'; etcmiv_data_rdy_detected <= '0'; ............ elsif(rising_edge(clk)) then if (..........) then ............ elsif(......) then if(.....) then ..... else if((etcmiv_data_rdy = '1') and (int_flash_en = '0')) then etcmiv_data_rdy_detected <= '1'; end if; if((clk_spi_flash = '1') and (int_flash_en = '0') and (etcmiv_data_rdy_detected = '1'))then int_flash_en <= '1'; etcmiv_data_rdy_detected <= '0'; ........ ....... else ...... int_flash_en <= '0'; ....... The only places in code where these two signals (int_flash_en and etcmiv_data_rdy_detected) are touched are listed above. When running on FPGA, I got a positive pulse on etcmiv_data_rdy_detected, but int_flash_en remains untouched ('0'). I was supposing etcmiv_data_rdy_detected should only go down together with int_flash_en assertion. Is my assumption wrong? Can anybody help me with some light on that? I am using Quartus II 9.1 web edition and ModelSim Altera Starter Edition 6.5b. My FPGA is a CycloneIII EP3C25Q240C8N Thanks in advance Cristiano13 Replies
Altera_ForumHello Cristiano, It might be better if you post your complete code to see where the problem is. From the above code you have posted, I do not see why your "int_flash_en" is not enabled when "etcmiv_data_rdy_detected" goes low. Please check your code if you have any other assignment for int_flash_en outside the process. Most likely it might be the case. all the best.
- Altera_Forum
Please post more code - the snippets you posted without indentation are rather confusing
On first glance - I worry whenever I see a signal called "clk" thats being checked in an if statement rather than being used as an actual clock. - Altera_Forum
Post the whole code, not just redacted sections. You most likely have a problem with your logic, but won't be able to tell unless everything is posted.
Kevin
