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Altera_Forum
Honored Contributor
Honored ContributorTip/suppornt on debugging a VHDL project on Altera
Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_ForumHonored Contributor
Honored ContributorPlease post more code - the snippets you posted without indentation are rather confusing
On first glance - I worry whenever I see a signal called "clk" thats being checked in an if statement rather than being used as an actual clock.
