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Altera_Forum
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16 years ago

Tip/suppornt on debugging a VHDL project on Altera

Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
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Altera_Forum
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16 years ago

Hello Cristiano, It might be better if you post your complete code to see where the problem is. From the above code you have posted, I do not see why your "int_flash_en" is not enabled when "etcmiv_data_rdy_detected" goes low. Please check your code if you have any other assignment for int_flash_en outside the process. Most likely it might be the case. all the best.