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Altera_Forum
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16 years ago

Tip/suppornt on debugging a VHDL project on Altera

Hi I have some experience on hdl coding, but none on FPGA debugging. (which does not necessarily mean the problem may not be in my HDL coding... ;) ) I´m facing a weird (imho) situation ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Post the whole code, not just redacted sections. You most likely have a problem with your logic, but won't be able to tell unless everything is posted.

Kevin