Honored ContributorDoes anybody know how to set timing requirements to a part of a circuit? I mean there is a critical part of a circuit that needs frequency optimization, and it's not rational to apply frequency constraint to all block. Thanks in advance.
Honored ContributorPlease could you clairfy? if your whole design is synchronous then you should just be able to set timing constraints to the clocks and it will do the work for you. Clock domain crossings need some consideration, but sometimes false paths are sufficient.
Honored ContributorI think it's not a good strategy to optimize whole design in each case. For example, let it consists of several clock domains. One of these domains contains a part which must be optimized (a lot of logic between FFs). Of course we can set a constraint to a whole domain, but from my point of view this approach could lead to a non-optimal routing of other parts of the design. I mean that one part of the domain might operate exactly with clock frequency, while others might use enables and their actual operating frequencies could be much lower then clock frequency, that's why those parts don't need optimization.
Honored ContributorYou can define multi cycle paths to allow the fitter more flexibility if such things exists. You can also place logic lock regions to restrict specific parts of the design to specific regions of the chip. This often has the effect of prioritising these parts within the area, and any other non-logic-locked logic will fit in around the locked areas. This will help your timing by keeping an entity close together rather than spreading it apart.
You should only consider this though if you are having problems with normal timing (ie. specify the clocks and then compile). using logic lock regions becomes very trial and error and can consume a lot of time.Honored ContributorThank you for your answer
Honored ContributorIn Altera's examples they set multicycle_path for enabled triggers and thus don't set timing requirements for them at all. However, sometimes this part of a project still needs timing requirements (maybe less strict). Is it possible set timing requirements for such piece of a project?
Another problem that I've faced is difficulties in specifying triggers to set multicycling option to if they are "buried" into the project's hierarchy.Honored ContributorHonored ContributorBut I don't see these triggers with relaxed constraints into the report. Now I'm working with Clock Enable Multicycle Constraints project from TimeQuest TA cookbook and the only regs I see are regs from pipelined mult (they are not enabled). I can find them into name finder but I don't know how to add them to the report...
Honored Contributorcan you copy that Altera sdc example and design here or provide a link so I can better understand your viewpoint
Honored ContributorHere you are
Honored Contributorsorry I can't run projects now but a diagram and sdc will do.
Anyway I looked at the TA cookbook/figure 1-16 clock enable multicycle on page 1-25 and all registers are enabled(those into mult and those at mult outputs). In such cases you can apply sdc command for enable only and you don't need to worry about each single register. Are you looking at same design?
