Timing requirements to a part of a circuit

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In Altera's examples they set multicycle_path for enabled triggers and thus don't set timing requirements for them at all. However, sometimes this part of a project still needs timing requirements (maybe less strict). Is it possible set timing requirements for such piece of a project?

Another problem that I've faced is difficulties in specifying triggers to set multicycling option to if they are "buried" into the project's hierarchy.

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In those examples the multicycle constraint is a timing constraint on all registers enabled by the enable signal. Without them setup relationship defaults to one clock period and hold to zero, with them you relax it e.g. to 2 for setup, 1 for hold or 3 for setup, 2 for hold.

A convenient way to locate the nodes is to run TQ and then go to node finder and copy its path and name.