Timing requirements to a part of a circuit

I think it's not a good strategy to optimize whole design in each case. For example, let it consists of several clock domains. One of these domains contains a part which must be optimized (a lot of logic between FFs). Of course we can set a constraint to a whole domain, but from my point of view this approach could lead to a non-optimal routing of other parts of the design. I mean that one part of the domain might operate exactly with clock frequency, while others might use enables and their actual operating frequencies could be much lower then clock frequency, that's why those parts don't need optimization.