Timing requirements to a part of a circuit

You can define multi cycle paths to allow the fitter more flexibility if such things exists. You can also place logic lock regions to restrict specific parts of the design to specific regions of the chip. This often has the effect of prioritising these parts within the area, and any other non-logic-locked logic will fit in around the locked areas. This will help your timing by keeping an entity close together rather than spreading it apart.

You should only consider this though if you are having problems with normal timing (ie. specify the clocks and then compile). using logic lock regions becomes very trial and error and can consume a lot of time.