Timing constraints for output clock pin

Question

I'm constraining a synchronous interface to a USB chip, and I've got all the timing constraints in for the data and control lines. Timequest is still listing the output clock itself as unconstrained. Do I need to constrain this? Ultimately as long as all the other constraints are met, I don't really care how much delay is present between the PLL clock output and the clock output pin. Should I set a false path to the output clock pin, or is there some other recommended thing to do?

Regards,

David

altera_forum · Answer

as you have realised clk output does not need constraints by itself. to keep timequest happy set false path:

set_false_path -to [get_ports {clkout}]

exception to that if you need to treat it as any nonclk output

altera_forum · Answer

Thanks kaz!

Forum Discussion

Timing constraints for output clock pin

2 Replies

Recent Discussions

Agilex5 A5EB013BB23BE4S BSDL

Avalon-ST configuration with Agilex 3 fails

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration