Timing constraints for output clock pin

I'm constraining a synchronous interface to a USB chip, and I've got all the timing constraints in for the data and control lines. Timequest is still listing the output clock itself as unconstrained. Do I need to constrain this? Ultimately as long as all the other constraints are met, I don't really care how much delay is present between the PLL clock output and the clock output pin. Should I set a false path to the output clock pin, or is there some other recommended thing to do?