Timing Closure for domain crossing between source and divided clocks

This post is an offshoot of an earlier post entitled

"Are divided clocks synchronous with the source clock?"

I have a cpld design with 5 different clock domains. There is a slow master clock (1.432MHz, T = 542ns), and 4 (integer) divided clocks generated from the master by separate synchronous counters. The positive edge of each divided clock should then be one Tco behind a positive edge of the source clock, and data in the divided clock domains should be another Tco delayed behind the positive edge of the divided clock. I assumed this was a fixed phase relationship that meant all these domains were synchronous. But Quartus doesn't agree.

I had warnings on every domain crossing: Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains

There were also hold time violations on signals transferred to the master clock domain. I got rid of these by clocking data out of the master clock domain on the negative edge of the master clock and into the slower domains on the positive edges of the divided clocks. That way there is always at least 270ns of setup and hold time in the divided clock domains.

The result of the above was a new warning: Warning (308022): (Medium) Rule C106: Clock signal source should not drive registers triggered by different clock edges. Is this something I need to be concerned about?

I do have generated clock constraints in my SDC file stating that the divided clocks are integer divisions of the master, but still have "Data bits not synchronized" warnings. Do I need to add synchronizers to every bit? I have synch'ed data ready flags and latched data when they are asserted, but Quartus is still unhappy.

Any help is greatly appreciated