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jch4416's avatar
jch4416
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing Closure for domain crossing between source and divided clocks

This post is an offshoot of an earlier post entitled "Are divided clocks synchronous with the source clock?" I have a cpld design with 5 different clock domains. There is a slow master clock (1....
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Can you show your .sdc and maybe a drawing of your clock network at this point? It's a little hard to visualize.

You're using such low clock speeds that it's surprising that you'd run into any timing issues, though I guess the hold timing issues may be more of a trampling of the next clock cycle by a previous one.