Occasional Contributor
Occasional ContributorHello,
Happy New Year and thanks for your help. I am attaching the sdc file and a pdf showing the clock tree structure. The clock definitions from the sdc are pasted below the dotted line
Jim
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#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports {clock_in_3p6864mhz}]
create_clock -name {cpld_master_clock} -period 542.000 -waveform { 0.000 271.000 } [get_nets {cpld_master_clock}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {uart_rx_clock} -source [get_nets {cpld_master_clock}] -divide_by 2 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV2|clk_out}]
create_generated_clock -name {uart_tx_clock} -source [get_nets {cpld_master_clock}] -divide_by 32 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV3|clk_out}]
create_generated_clock -name {millisec_clock} -source [get_nets {cpld_master_clock}] -divide_by 1920 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV4|clk_out}]
create_generated_clock -name {heartbeat_clock} -source [get_nets {cpld_master_clock}] -divide_by 3840 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV5|clk_out}]
Super ContributorYour second create_clock should be a create_generated_clock since it's sourced from the input clock. And you should always try to use get_pins for your targets instead of get_nets. You can use the Name Finder through the Quartus Text Editor SDC GUI dialog boxes to find the correct targets.
Occasional ContributorThanks for your reply. I am trying to implement your advice, but so far unsuccessfully.
I used the post-fit netlist viewer to try to figure out the correct names. Here are the constraints I created in the Timing Analyzer using the post-fit names:
create_generated_clock -name {cpld_master_clock} -source [get_ports {clock_in_3p6864mhz}] -divide_by 2 -master_clock {clock_in_3p6864mhz} [get_pins {CDIV1|clk_in_count[0]|regout}]
create_generated_clock -name {uart_rx_clock} -source [get_pins {cpld_master_clock|combout}] -divide_by 2 -master_clock {clock_divider:CDIV1|clk_out} [get_pins {CDIV2|clk_out|regout}]
create_generated_clock -name {uart_tx_clock} -source [get_pins {cpld_master_clock|combout}] -divide_by 16 -master_clock {clock_divider:CDIV1|clk_out} [get_pins {CDIV3|clk_out|regout}]
create_generated_clock -name {millisec_clock} -source [get_pins {cpld_master_clock|combout}] -divide_by 1920 -master_clock {clock_divider:CDIV1|clk_out} [get_pins {CDIV4|clk_out|regout}]
create_generated_clock -name {heartbeat_clock} -source [get_pins {cpld_master_clock|combout}] -divide_by 2 -master_clock {clock_divider:CDIV1|clk_out} [get_pins {CDIV5|clk_out|regout}]
The Quartus fitter rejected all but the first one. The error messages are below:
Info (332104): Reading SDC File: 'Mk1_Safety_Unit_CPLD.out.sdc'
Warning (332087): The master clock for this clock assignment could not be derived. Clock: uart_rx_clock was not created.
Warning (332034): Specified master clock: clock_divider:CDIV1|clk_out not found on or feeding the specified source node: cpld_master_clock|combout
Warning (332087): The master clock for this clock assignment could not be derived. Clock: uart_tx_clock was not created.
Warning (332034): Specified master clock: clock_divider:CDIV1|clk_out not found on or feeding the specified source node: cpld_master_clock|combout
Warning (332087): The master clock for this clock assignment could not be derived. Clock: millisec_clock was not created.
Warning (332034): Specified master clock: clock_divider:CDIV1|clk_out not found on or feeding the specified source node: cpld_master_clock|combout
Warning (332087): The master clock for this clock assignment could not be derived. Clock: heartbeat_clock was not created.
Warning (332034): Specified master clock: clock_divider:CDIV1|clk_out not found on or feeding the specified source node: cpld_master_clock|combout
Warning (332060): Node: clock_divider:CDIV1|clk_out was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: clock_divider:CDIV3|clk_out was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: clock_divider:CDIV2|clk_out was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: clock_divider:CDIV5|clk_out was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: clock_divider:CDIV4|clk_out was determined to be a clock but was found without an associated clock assignment.
I think I'm on the right track, but I don't yet have the names that the fitter wants to see for the -source_clock and/or -master_clock fields.
I am attaching a screenshot of the post-fit netlist viewer output showing the output of CDIV1 and the global buffer that follows it. The global buffer output feeds dividers CDIV2-5 but what should I use as the source pin in the constraints for CDIV2-5? Apparently cpld_master_clock|combout isn't right.
Occasional ContributorI made some progress. Saw an error in the target pin for the cpld_master_clock and corrected it. Also changed the source clock definition for each divider from -source [get_pins {cpld_master_clock|combout}] to -source [get_nets {cpld_master_clock}].
Why would get_pins{ } be better than get_nets{ }?
Quartus was happy with this and all the synchronization warnings disappeared.
The constraints are now:
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clock_in_3p6864mhz} -period 271.000 -waveform { 0.000 135.000 } [get_ports {clock_in_3p6864mhz}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {cpld_master_clock} -source [get_ports {clock_in_3p6864mhz}] -divide_by 2 -master_clock {clock_in_3p6864mhz} [get_pins {CDIV1|clk_out|regout}]
create_generated_clock -name {uart_rx_clock} -source [get_nets {cpld_master_clock}] -divide_by 2 -master_clock {cpld_master_clock} [get_pins {CDIV2|clk_out|regout}]
create_generated_clock -name {uart_tx_clock} -source [get_nets {cpld_master_clock}] -divide_by 32 -master_clock {cpld_master_clock} [get_pins {CDIV3|clk_out|regout}]
create_generated_clock -name {millisec_clock} -source [get_nets {cpld_master_clock}] -divide_by 1920 -master_clock {cpld_master_clock} [get_pins {CDIV4|clk_out|regout}]
create_generated_clock -name {heartbeat_clock} -source [get_nets {cpld_master_clock}] -divide_by 2048 -master_clock {cpld_master_clock} [get_pins {CDIV5|clk_out|regout}]
Super ContributorFirst, you don't need the master_clock option. That's only needed if there are multiple clocks at the source for a generated clock.
Second, you can't use the netlist viewer to get the correct SDC targets. Use the Name Finder found in any of the GUI dialog boxes you can access from the Edit menu when you're editing a .sdc file in the Quartus Text Editor.
I recommend get_pins because it is always a physical node in the design and there's less chance the name may change.
Glad you cleared the errors.
