New Contributortiming analyzer 21.1 pro : missing clock delay at clock output port
Hi,
I am using the Timing Analyzer of Quartus Prime 21-1 Pro.
I have to constrain a source synchronous interface and a questions arose while observing the setup timing report.
In my design (see attached screenshot) the output of my pll feeds:
. a FF, which data is then sent to an output port (LOSI.MOSI)
. an output port, used as clock for my synchronous interface (LOSI.CLK)
The timing constraints are:
. PLL clocks are generated automatically, therefore I do not write them explicitly (not even the base clock)
. I generate a clock from the PLL out
create_generated_clock -name LOSI_CLK_OUT \
-source [get_pins {rcv_s10_top|sys_clk_rst|sw_pll|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] \
[get_ports {losi.clk*}]
. I set an output delay based on that clock
set_output_delay -clock LOSI_CLK_OUT -max $my_delay [get_ports {losi.mosi*}]
PROBLEM: When i check the setup relation on the MOSI pin, I do not see the clock network delay at the data required path.. that seems wrong!!
report_timing -to [get_ports {losi.mosi}] -setup -detail full_path
See the screenshot setup_timing.
I would have expected to see at least 4-5 ns of clock network delay, similar to the clock of the MOSI FF, but there is 0, as the clock was virtual and not generated.
Can anybody help?
Regards,
Rob.
UPDATE: the issue was solved and was due to a TCL variable set with the same name of the generated clock.
