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pRob's avatar
pRob
Icon for New Contributor rankNew Contributor
4 years ago

timing analyzer 21.1 pro : missing clock delay at clock output port

Hi, I am using the Timing Analyzer of Quartus Prime 21-1 Pro. I have to constrain a source synchronous interface and a questions arose while observing the setup timing report. In my design (see...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


It's possible that Timing Analyzer is ignoring the constraint. Could you Report Ignored Constraints and see which constraints are being ignored?


Additionally could you provide your .qar file of your project? To generate a .qar file, go to Projects>Archive Project


Regards,

Nurina