timing analyzer 21.1 pro : missing clock delay at clock output port

The 'update' in the Post is wrong. I'd like to remove that line in the post but it seems not possible anymore.

The issue was solved not by reordering the TCL variables in my code but by changing the clock definition.

This is the erratic code:

create_generated_clock -name LOSI_CLK_OUT \
  -source [get_pins {rcv_s10_top|sys_clk_rst|sw_pll|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] \
  [get_ports {losi.clk*}]

As I am using differential inputs therefore i generated one single clock for both P and N input.

This has confused the Timing Analyzer leading to the wrong timing report attached.

The solution was to define a single clock at the P pin (see the attached screenshot):

create_generated_clock -name LOSI_CLK_OUT \
  -source [get_pins {rcv_s10_top|sys_clk_rst|sw_pll|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll|outclk[0]}] \
  [get_ports {losi.clk}]

I am not fully sure if this is a bug or a known limitation in Timing Analyzer. If someone can confirm my finding I could consider opening a ticket (bug)