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pRob's avatar
pRob
Icon for New Contributor rankNew Contributor
4 years ago

timing analyzer 21.1 pro : missing clock delay at clock output port

Hi, I am using the Timing Analyzer of Quartus Prime 21-1 Pro. I have to constrain a source synchronous interface and a questions arose while observing the setup timing report. In my design (see...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,


We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,

Nurina


P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!