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pRob's avatar
pRob
Icon for New Contributor rankNew Contributor
4 years ago

timing analyzer 21.1 pro : missing clock delay at clock output port

Hi, I am using the Timing Analyzer of Quartus Prime 21-1 Pro. I have to constrain a source synchronous interface and a questions arose while observing the setup timing report. In my design (see...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


I'm glad to hear that your problem is solved. Can you share your solution so that it may help others in the future?


Thanks and regards,

Nurina