Dear All, is it possible to use generic of type 'time' in an entity declaration which is used for synthesis? I'd like to use time specification as top-entity generic parameter, which is in the sub-entity recalculated to integer and hence it is fully synthesizable (recalculation using e.g. 100 ns / 25 ns leads to integer right?). This works great in simulation, however quartus refuses to instantiate block claiming that 's' does not exist: entity top_entity is generic ( DELAY_LINE_DEPTH : integer := 8; --! default FIFO used for BLR RESET_PULSE_LENGTH : integer := 50; --! length of automatically generated reset BCF_DEFAULT_THRESHOLD_VALUE : integer := 3700; --! default value of threshold loaded when register is reset MAX6627_AUTORUN : time := 2s); --! autorun of max circuit

--- Quote Start --- Dear All, is it possible to use generic of type 'time' in an entity declaration which is used for synthesis? I'd like to use time specification as top-entity generic parameter, which is in the sub-entity recalculated to integer and hence it is fully synthesizable (recalculation using e.g. 100 ns / 25 ns leads to integer right?). This works great in simulation, however quartus refuses to instantiate block claiming that 's' does not exist: entity top_entity is generic ( DELAY_LINE_DEPTH : integer := 8; --! default FIFO used for BLR RESET_PULSE_LENGTH : integer := 50; --! length of automatically generated reset BCF_DEFAULT_THRESHOLD_VALUE : integer := 3700; --! default value of threshold loaded when register is reset MAX6627_AUTORUN : time := 2s); --! autorun of max circuit --- Quote End --- Hi, I'm not a VHDL expert, but what would you like to achieve ? Should your design run for a certain time ? King regards GPK

no. the achievement would be to calculate various variables in unconstrained way. Imagine you have entity generating clock enable after X clock cycles. If your clock is a generic as well (so say you define XOSC_CLK : time := 25ns), then you can specify various time constants in the design in terms of time. In case of the clock enable generator you would say that you wish to generate clock enable every 100us, hence the generic input to this entity would be TICKS_WAIT : integer := 100 us / XOSC_CLK. In standard way this situation is solved using integers because apparently clock division does not work in quartus synthesis (besides the fact the division of two times results in integer and thus fully synthesizable unit). Then you have to pass as generic something like TICKS_WAIT : integer := 4000. While the definition of generic by time would bring you clear understanding what you're setting, number of ticks is in integer is not so clear.

I don't think it is synthesizable. You can still use integers but use them as values in us/ns instead of clock ticks. As long as you comment what time unit you are using it should be almost as understandable.

Time can be used quite happily as a generic, but you'll only be able to derrive constants from it, or use it in generate statements. You cannot use time to specify clocks or anything else like it (like the time between enables) in synthesis. In simulation it will be fine, but synthesis has no understanding of time. The way you space out enables is to count your incoming clock ticks and toggling the enable appropriatly. All of the below examples are not synthesisable, or are simply ignored in synthesis: enable <= '0', '1' after 10 ns; (the after case is ignored, will just set enable to '0') enable <= enable_in after 50 ns; (again, enable is just a wire) wait for 10 ns; (will throw an error)

Hi Tricky, frankly, I do not understand why following construct should make any problems to synthesizer (however meaningless the example is): entity mystuff is generic (XOSC : time := 25 ns; DELAY_TO_OUTPUT : time := 2 us); port (ClkxC : in std_logic; ResetxRNA : in std_logic; QxS : out std_logic); end entity mystuff; architecture v1 of mystuff is constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC; component clock_divider is generic (DIVIDER : integer); port (ClkxC : in std_logic; pResetxRNA : in std_logic; ClkxE : out std_logic); end component clock_divider; begin -- architecture v1 DIDI : clock_divider generic map (DIVIDER => NUMTICKS) port map (ClkxC => ClkxC, pResetxRNA => ResetxRNA, ClkxE => QxS); end architecture v1; IMHO this is fully synthesizable as division of two time units is unitless hence could be casted to integer and it is really clear what the synthesizer should do with that. Am I right? d.

time in generic clause of entity for synthesis

13 Replies

Altera_Forum
Honored Contributor
16 years ago
Confirmed. 1sec works in Q9.1, so modelsim extends the standard behaviour

thanks for clarification

d.
Altera_Forum
Honored Contributor
16 years ago
According to my STANDARD library, the name of the second unit is 'sec' and not 's'... even if all the other units are 'ms' 'us' 'ns' etc...
So it seems that Modelsim is doing more than the standard.
Altera_Forum
Honored Contributor
16 years ago
Id raise a support request with altera about this.
Altera_Forum
Honored Contributor
16 years ago
I just wanted to re-open this subject because I've found why it does not compile.

In my original designs I have used '1 s' to declare the time generic. This did not compile with quartus. It always ended with 'unknown symbol 's''. However when the 1s is replaced by '1000 ms', everything compiles fine.

As '1s' declaration works well in modelsim, it seems that quartus compiler does not recognize '1s' as 'one-second', but as a number associated with some symbol/variable.
Altera_Forum
Honored Contributor
16 years ago
best to just stick in VHDL for your top level instantiations.

Yeah! That would be my ultimate goal into the future. I've taken over this design so I have to live with it as it is now :(

Thanks a lot. That explains it.

d.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
sorry. i've been talking about syntesis, but in fact I tried create a symbol block. This is where it crashes. (q9.0)

d.
--- Quote End ---

Well that will be your problem.

The symbol creator is very basic and wont accept anything too exciting. It can only really cope with integers, signed/unsigned, std_logic(_vector) and boolean.

best to just stick in VHDL for your top level instantiations.
Altera_Forum
Honored Contributor
16 years ago
sorry. i've been talking about syntesis, but in fact I tried create a symbol block. This is where it crashes. (q9.0)

d.

Altera_Forum

Honored Contributor

16 years ago

yup - your idea synthesises fine.

here is some code I just synthesised fine in Q9.1 SP1


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity test_build is
  generic (XOSC : time := 25 ns;
    DELAY_TO_OUTPUT : time := 2 us
  );
  
    port (
      ------------------------------
      --Clock and reset
      ------------------------------      
      clk       : in  std_logic;
      
      a         : in std_logic;
      b         : out std_logic
    );
end entity;
architecture rtl of test_build is
  constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC;
  signal dly : std_logic_vector(NUMTICKS-1 downto 0);
begin
  
  
  process(clk)
  begin
    if rising_edge(clk) then
      
      dly <= dly(dly'high-1 downto 0) & a;
      
      b <= dly(dly'high);
      
    end if;
  end process;  
  
end architecture rtl;

Altera_Forum
Honored Contributor
16 years ago
Hi Tricky,
frankly, I do not understand why following construct should make any problems to synthesizer (however meaningless the example is):

entity mystuff is
generic (XOSC : time := 25 ns;
DELAY_TO_OUTPUT : time := 2 us);
port (ClkxC : in std_logic;
ResetxRNA : in std_logic;
QxS : out std_logic);
end entity mystuff;

architecture v1 of mystuff is

constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC;
component clock_divider is
generic (DIVIDER : integer);
port (ClkxC : in std_logic;
pResetxRNA : in std_logic;
ClkxE : out std_logic);
end component clock_divider;

begin -- architecture v1
DIDI : clock_divider
generic map (DIVIDER => NUMTICKS)
port map (ClkxC => ClkxC,
pResetxRNA => ResetxRNA,
ClkxE => QxS);
end architecture v1;

IMHO this is fully synthesizable as division of two time units is unitless hence could be casted to integer and it is really clear what the synthesizer should do with that. Am I right?

d.
Altera_Forum
Honored Contributor
16 years ago
Time can be used quite happily as a generic, but you'll only be able to derrive constants from it, or use it in generate statements.

You cannot use time to specify clocks or anything else like it (like the time between enables) in synthesis. In simulation it will be fine, but synthesis has no understanding of time. The way you space out enables is to count your incoming clock ticks and toggling the enable appropriatly.

All of the below examples are not synthesisable, or are simply ignored in synthesis:

enable <= '0', '1' after 10 ns; (the after case is ignored, will just set enable to '0')
enable <= enable_in after 50 ns; (again, enable is just a wire)
wait for 10 ns; (will throw an error)

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time in generic clause of entity for synthesis

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