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Altera_Forum
Honored Contributor
15 years agoTime can be used quite happily as a generic, but you'll only be able to derrive constants from it, or use it in generate statements.
You cannot use time to specify clocks or anything else like it (like the time between enables) in synthesis. In simulation it will be fine, but synthesis has no understanding of time. The way you space out enables is to count your incoming clock ticks and toggling the enable appropriatly. All of the below examples are not synthesisable, or are simply ignored in synthesis: enable <= '0', '1' after 10 ns; (the after case is ignored, will just set enable to '0') enable <= enable_in after 50 ns; (again, enable is just a wire) wait for 10 ns; (will throw an error)