time in generic clause of entity for synthesis

yup - your idea synthesises fine.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity test_build is
  generic (XOSC : time := 25 ns;
    DELAY_TO_OUTPUT : time := 2 us
  );
  
    port (
      ------------------------------
      --Clock and reset
      ------------------------------      
      clk       : in  std_logic;
      
      a         : in std_logic;
      b         : out std_logic
    );
end entity;
architecture rtl of test_build is
  constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC;
  signal dly : std_logic_vector(NUMTICKS-1 downto 0);
begin
  
  
  process(clk)
  begin
    if rising_edge(clk) then
      
      dly <= dly(dly'high-1 downto 0) & a;
      
      b <= dly(dly'high);
      
    end if;
  end process;  
  
end architecture rtl;