time in generic clause of entity for synthesis

Hi Tricky,

frankly, I do not understand why following construct should make any problems to synthesizer (however meaningless the example is):

entity mystuff is

generic (XOSC : time := 25 ns;

DELAY_TO_OUTPUT : time := 2 us);

port (ClkxC : in std_logic;

ResetxRNA : in std_logic;

QxS : out std_logic);

end entity mystuff;

architecture v1 of mystuff is

constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC;

component clock_divider is

generic (DIVIDER : integer);

port (ClkxC : in std_logic;

pResetxRNA : in std_logic;

ClkxE : out std_logic);

end component clock_divider;

begin -- architecture v1

DIDI : clock_divider

generic map (DIVIDER => NUMTICKS)

port map (ClkxC => ClkxC,

pResetxRNA => ResetxRNA,

ClkxE => QxS);

end architecture v1;

IMHO this is fully synthesizable as division of two time units is unitless hence could be casted to integer and it is really clear what the synthesizer should do with that. Am I right?

d.