Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- sorry. i've been talking about syntesis, but in fact I tried create a symbol block. This is where it crashes. (q9.0) d. --- Quote End --- Well that will be your problem. The symbol creator is very basic and wont accept anything too exciting. It can only really cope with integers, signed/unsigned, std_logic(_vector) and boolean. best to just stick in VHDL for your top level instantiations.