time in generic clause of entity for synthesis

no. the achievement would be to calculate various variables in unconstrained way. Imagine you have entity generating clock enable after X clock cycles. If your clock is a generic as well (so say you define XOSC_CLK : time := 25ns), then you can specify various time constants in the design in terms of time. In case of the clock enable generator you would say that you wish to generate clock enable every 100us, hence the generic input to this entity would be TICKS_WAIT : integer := 100 us / XOSC_CLK.

I don't think it is synthesizable. You can still use integers but use them as values in us/ns instead of clock ticks. As long as you comment what time unit you are using it should be almost as understandable.

Time can be used quite happily as a generic, but you'll only be able to derrive constants from it, or use it in generate statements.

Hi Tricky,

yup - your idea synthesises fine.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity test_build is
  generic (XOSC : time := 25 ns;
    DELAY_TO_OUTPUT : time := 2 us
  );
  
    port (
      ------------------------------
      --Clock and reset
      ------------------------------      
      clk       : in  std_logic;
      
      a         : in std_logic;
      b         : out std_logic
    );
end entity;
architecture rtl of test_build is
  constant NUMTICKS : integer := DELAY_TO_OUTPUT / XOSC;
  signal dly : std_logic_vector(NUMTICKS-1 downto 0);
begin
  
  
  process(clk)
  begin
    if rising_edge(clk) then
      
      dly <= dly(dly'high-1 downto 0) & a;
      
      b <= dly(dly'high);
      
    end if;
  end process;  
  
end architecture rtl;

sorry. i've been talking about syntesis, but in fact I tried create a symbol block. This is where it crashes. (q9.0)

best to just stick in VHDL for your top level instantiations.

I just wanted to re-open this subject because I've found why it does not compile.