The Hype of SoC's

I come from the software side and I think it is awesome to have the arm processors.

It provides me with an entry point and a path to upgrade the performance of my system. It is starting off with minimal signal processing done on the fpga and as I get more demand I'll try to offload more to the fpga.

titantomorrow

Thanks for responding to my post. Do you have any experience with Altera's ARM+FPGA devices? Have you developed any applications? I'd like to know if you found it "painful" or "painless"? I agree with your observations on the possibilities of these devices but the complexity of the tools and the inadequate documentation I have a hard time believing any designer will quickly choose these devices in the designs. It would be less risky to keep these two worlds (ARM,FPGA) separate and spend your energies getting a high-speed serial link working between the two devices to pass critical data. As I said in the start of this post I'm enthusiastic about these devices but after seeing my co-working spend months only on the FPGA development I can't see any program manager supporting such an endeavor. That's why I really believe that Altera must have something better waiting in the wings when the Stratix 10 is released. However, the more I hear from others in the communities the more informed I'll be and my change my opinions, so please share your thoughts.

I have a long history with both Quartus and ISE. Between those two tools I agree that I much preferred Quartus. Better integrated, easier to use. SignalTap was a big part of that. Much easier to use than ChipScope.

About a year ago we started a new platform targeting a Zynq device with Vivado. Got pretty far down the development path on a ZC706 dev kit, but due to some pricing issues and limitations of the Zynq silicon (no DDR4, no PCIe gen 3, etc) we jumped ship over to Arria 10 SoC and Quartus Prime. Compared to Vivado, Quartus Prime feels quite outdated and cobbled together. I found Vivado's IP Integrator vastly superior to Qsys, which is a pretty primitive tool by comparison. And the way Vivado handles IP is consistent and very well thought out. Quartus is way behind in that regard. Xilinx is also light years ahead of Altera in terms of documentation (quantity, quality, ease of management with DocNav) and in the availabiliy and quality of reference designs.

As for development communities, as mentioned by sveinse above, this forum is a ghost town compared to Xilinx'x user forum. Especially for SoC designs. I've posted a few Arria 10 SoC questions here and don't think I've ever gotten a response. Xilinx staffs their user forum with a whole team of employees who monitor the forums and answer questions quickly. On this forum there is very little company support. We knew we were early adopters with Arria 10 SoC, but it really feels like we're flying solo. So far the Arria 10 silicon looks awesome vs. Zynq. But tools and support are critical and Altera is way behind Xilinx in those areas. It's not even close.

Back to the title of this thread, there is a lot of hype with SoCs. Both Altera and Xilinx are pushing hard on the idea that any old software dude with no FPGA experience can describe a system in C code, push a few buttons, and voila! Well, it's never going to be that simple. If all you need is a processor and a few peripherals then no problem. But integrating a hard processor with a complex FPGA design on an SoC is not much different than it was with a separate processor and FPGA. In fact in some ways it's harder because the tools and methodology are geared toward the Qsys/IP Integrator approach. That's where hype meets reality.

I think you have answered your own question: If you need the IP to work across vendors, dont use Avalon. Annoyingly though, if you want to connect to any Altera IP, it will have Avalon interfaces.

Luckily, Altera provides AXI->Avalon converters for everything except streaming (which isnt that difficult to do yourself - its just a FIFO with some extra control logic).

So - always going to use altera - use avalon. Using anything else - go with AXI.

sveinse - If you're designing custom IP for your own use then I would probably not use Avalon, but it depends on what you're doing. I understand the benefits of AXI and Avalon as standard interfaces, but I would never design an entire system around either bus. It may seem convenient to stitch a bunch of blocks together in Qsys or IP Integrator (Vivado) and not have to think about the details, but have you ever looked at how much logic gets consumed uunder the covers as the tools do the stitching? Width conversions, protocol conversions, clock domain crossing, muxing/demuxing, etc. I prefer to have more control over my designs and not have so much crap inserted by the tools that I have little or no control over. And it's not just the extra logic. The inserted logic doesn't always give you the best performance.

I typically only use Qsys or IP Intergator to instantiate and configure the HPS and whatver blocks need to interface directly to the HPS. I export the AXI or Avalon interfaces I need to connect to the rest of the FPGA design and I'm then done with that part of the system. The rest is normal HDL design (verilog in my case). I then create a top-level verilog wrapper that instantiates my logic and the HPS/Qsys wad and hooks everything up. I'm not saying that's the only way or the right way to do things but it works for me. As I said above, it's a control thing. The more you depend on the tools the less able you are to debug and fix things when they go wrong.

Hi Joe, I've new to this world of FPGA and have not done much at all.

I come from a software development background (although I have a computer systems engineering degree), but I do know a bit about F# (declarative language) so it is actually not too different to HDL. After going through many of the tutorials and training videos, I think I am getting a handle on FPGA. However, it seems closing timing is a bit of black art.

At the moment, I'm not suffering too much from lack of documentation. But then again, I'm yet to find anything that is well documented. In a strange way I think the lack of documentation forces us to figure stuff out so in the long term it is good. Learning is quite steep and painful, but I'm focusing on the rewards.

I know what you mean, it requires a leap of faith. Having the two technologies closely coupled benefits me trying to do it all and not worrying about the best way to connect the two devices. Although there is a clear line of separation in the soc-fpga devices, I can just see the politics between the software and hardware developers emerging.