Hi Joe, I've new to this world of FPGA and have not done much at all.
I come from a software development background (although I have a computer systems engineering degree), but I do know a bit about F# (declarative language) so it is actually not too different to HDL. After going through many of the tutorials and training videos, I think I am getting a handle on FPGA. However, it seems closing timing is a bit of black art.
At the moment, I'm not suffering too much from lack of documentation. But then again, I'm yet to find anything that is well documented. In a strange way I think the lack of documentation forces us to figure stuff out so in the long term it is good. Learning is quite steep and painful, but I'm focusing on the rewards.
I know what you mean, it requires a leap of faith. Having the two technologies closely coupled benefits me trying to do it all and not worrying about the best way to connect the two devices. Although there is a clear line of separation in the soc-fpga devices, I can just see the politics between the software and hardware developers emerging.