The Hype of SoC's

sveinse - If you're designing custom IP for your own use then I would probably not use Avalon, but it depends on what you're doing. I understand the benefits of AXI and Avalon as standard interfaces, but I would never design an entire system around either bus. It may seem convenient to stitch a bunch of blocks together in Qsys or IP Integrator (Vivado) and not have to think about the details, but have you ever looked at how much logic gets consumed uunder the covers as the tools do the stitching? Width conversions, protocol conversions, clock domain crossing, muxing/demuxing, etc. I prefer to have more control over my designs and not have so much crap inserted by the tools that I have little or no control over. And it's not just the extra logic. The inserted logic doesn't always give you the best performance.

I typically only use Qsys or IP Intergator to instantiate and configure the HPS and whatver blocks need to interface directly to the HPS. I export the AXI or Avalon interfaces I need to connect to the rest of the FPGA design and I'm then done with that part of the system. The rest is normal HDL design (verilog in my case). I then create a top-level verilog wrapper that instantiates my logic and the HPS/Qsys wad and hooks everything up. I'm not saying that's the only way or the right way to do things but it works for me. As I said above, it's a control thing. The more you depend on the tools the less able you are to debug and fix things when they go wrong.