testbench integer type

I replace the integer value from "3" to 3 and "12" to 12 and its okay.

But, know i has another error:

Error (10533): VHDL Wait Statement error at reg_tb.vhd(37): Wait Statement must contain condition clause with UNTIL keyword

Most of the testbench code that I has study uses Wait statement without UNTIL keyword..I'm confuse know..Anyone help me please.

Many thanks

You should have a space between 100 and ns but that should just issue a warning, not an error.

Are you sure this file is marked as a testbench and isn't run through the synthesizer?

Dear Daixiwen,

I already fix the error. I run simulate the testbench code in ModelSim and its okay.

I has one question, how to make a testbench when we have several subcode.

For example, I has four vhd file:

(1)reg.vhd (2)adddiv.vhd (3)difference.vhd (4)haar.vhd

where haar.vhd is the main file of the program.

I want to make testbench for the main file.

Many thanks

Dear Tricky,

I has instantiate the haar.vhd file and also compile all others file in to library.

But, when I run it, the input is correct but no output is obtained. I don't know why. Below is my haar testbench code:

---------------------------------------------------------------------------

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

entity haar_tb is

end;

architecture bench of haar_tb is

-------------Component Declarations---------------

component haar

PORT (

clock : IN bit;

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

in4 : IN integer RANGE -127 TO 127;

in5 : IN integer RANGE -127 TO 127;

in6 : IN integer RANGE -127 TO 127;

in7 : IN integer RANGE -127 TO 127;

in8 : IN integer RANGE -127 TO 127;

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

out4 : OUT integer RANGE -127 TO 127;

out5 : OUT integer RANGE -127 TO 127;

out6 : OUT integer RANGE -127 TO 127;

out7 : OUT integer RANGE -127 TO 127;

out8 : OUT integer RANGE -127 TO 127

);

end component;

--------------Signal Declarations-----------------

signal clock: bit;

signal in1: integer RANGE -127 TO 127;

signal in2: integer RANGE -127 TO 127;

signal in3: integer RANGE -127 TO 127;

signal in4: integer RANGE -127 TO 127;

signal in5: integer RANGE -127 TO 127;

signal in6: integer RANGE -127 TO 127;

signal in7: integer RANGE -127 TO 127;

signal in8: integer RANGE -127 TO 127;

signal out1: integer RANGE -127 TO 127;

signal out2: integer RANGE -127 TO 127;

signal out3: integer RANGE -127 TO 127;

signal out4: integer RANGE -127 TO 127;

signal out5: integer RANGE -127 TO 127;

signal out6: integer RANGE -127 TO 127;

signal out7: integer RANGE -127 TO 127;

signal out8: integer RANGE -127 TO 127 ;

begin

---------------Component Instantiation--------------

uut: haar

port map ( clock => clock,

in1 => in1,

in2 => in2,

in3 => in3,

in4 => in4,

in5 => in5,

in6 => in6,

in7 => in7,

in8 => in8,

out1 => out1,

out2 => out2,

out3 => out3,

out4 => out4,

out5 => out5,

out6 => out6,

out7 => out7,

out8 => out8 );

stimulus: process

begin

---------------------First Test------------------

in1 <= 18;

in2 <= 5;

in3 <= 1;

in4 <= 9;

in5 <= 13;

in6 <= 6;

in7 <= 2;

in8 <= 3;

wait for 50ns;

---------------------Second Test------------------

in1 <= 10;

in2 <= 2;

in3 <= 3;

in4 <= 4;

in5 <= 15;

in6 <= 7;

in7 <= 13;

in8 <= 8;

wait for 50ns;

---------------------Third Test--------------------

in1 <= 1;

in2 <= 3;

in3 <= 11;

in4 <= 8;

in5 <= 15;

in6 <= 4;

in7 <= 6;

in8 <= 13;

wait for 50ns;

wait;

end process;

end;

Can you tell me, what I'm missing...Many thanks

Dear Tricky,

The run length is 1000ns. Yes, when I simulate the haar.vhd in Quartus there is no problem. The outputs is obtained correctly. Below is my haar.vhd code:

---------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.ALL;

ENTITY haar IS

PORT (

clock : IN bit;

-- Inputs

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

in4 : IN integer RANGE -127 TO 127;

in5 : IN integer RANGE -127 TO 127;

in6 : IN integer RANGE -127 TO 127;

in7 : IN integer RANGE -127 TO 127;

in8 : IN integer RANGE -127 TO 127;

--Outputs

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

out4 : OUT integer RANGE -127 TO 127;

out5 : OUT integer RANGE -127 TO 127;

out6 : OUT integer RANGE -127 TO 127;

out7 : OUT integer RANGE -127 TO 127;

out8 : OUT integer RANGE -127 TO 127

);

END haar;

ARCHITECTURE haar OF haar IS

COMPONENT reg

PORT (

input : IN integer RANGE -127 TO 127;

clk : IN bit;

output : OUT integer RANGE -127 TO 127

);

END COMPONENT;

COMPONENT adddiv

PORT (

a : IN integer RANGE -127 TO 127;

b : IN integer RANGE -127 TO 127;

clk : IN bit;

c : OUT integer RANGE -127 TO 127

);

END COMPONENT;

COMPONENT difference

PORT (

a : IN integer RANGE -127 TO 127;

b : IN integer RANGE -127 TO 127;

clk : IN bit;

c : OUT integer RANGE -127 TO 127

);

END COMPONENT;

SIGNAL out_r1, out_r2, out_r3, out_r4, out_r5, out_r6, out_r7,

out_r8, out_r9, out_r10, out_r11, out_r12, out_r13, out_r14,

out_r15, out_r16, out_r17, out_r18, out_r19, out_r20, out_r21,

out_r22, out_r23, out_r24 : integer RANGE -127 TO 127;

SIGNAL out_a1, out_a2, out_a3, out_a4, out_a5, out_a6, out_a7 : integer RANGE -127 TO 127;

SIGNAL out_s1, out_s2, out_s3, out_s4, out_s5, out_s6, out_s7 : integer RANGE -127 TO 127;

SIGNAL clk : bit;

BEGIN

-- Input to Register 1

r1: reg

PORT MAP ( in1, clk, out_r1 );

r2: reg

PORT MAP ( in2, clk, out_r2 );

r3: reg

PORT MAP ( in3, clk, out_r3 );

r4: reg

PORT MAP ( in4, clk, out_r4 );

r5: reg

PORT MAP ( in5, clk, out_r5 );

r6: reg

PORT MAP ( in6, clk, out_r6 );

r7: reg

PORT MAP ( in7, clk, out_r7 );

r8: reg

PORT MAP ( in8, clk, out_r8 );

-- Input to Add_Divide and Difference for stage 1

a1: adddiv

PORT MAP ( out_r1, out_r2, clk, out_a1 );

a2: adddiv

PORT MAP ( out_r3, out_r4, clk, out_a2 );

a3: adddiv

PORT MAP ( out_r5, out_r6, clk, out_a3 );

a4: adddiv

PORT MAP ( out_r7, out_r8, clk, out_a4 );

s1: difference

PORT MAP ( out_r1, out_r2, clk, out_s1 );

s2: difference

PORT MAP ( out_r3, out_r4, clk, out_s2 );

s3: difference

PORT MAP ( out_r5, out_r6, clk, out_s3 );

s4: difference

PORT MAP ( out_r7, out_r8, clk, out_s4 );

--Input to Register 2

r9: reg

PORT MAP ( out_a1, clk, out_r9 );

r10: reg

PORT MAP ( out_a2, clk, out_r10 );

r11: reg

PORT MAP ( out_a3, clk, out_r11 );

r12: reg

PORT MAP ( out_a4, clk, out_r12 );

r13: reg

PORT MAP ( out_s1, clk, out_r13 );

r14: reg

PORT MAP ( out_s2, clk, out_r14 );

r15: reg

PORT MAP ( out_s3, clk, out_r15 );

r16: reg

PORT MAP ( out_s4, clk, out_r16 );

-- Input to AddDiv and Difference for stage 2

a5: adddiv

PORT MAP ( out_r9, out_r10, clk, out_a5 );

a6: adddiv

PORT MAP ( out_r11, out_r12, clk, out_a6 );

s5: difference

PORT MAP ( out_r9, out_r10, clk, out_s5 );

s6: difference

PORT MAP ( out_r11, out_r12, clk, out_s6 );

--Input to Register 3

r17: reg

PORT MAP ( out_a5, clk, out_r17 );

r18: reg

PORT MAP ( out_a6, clk, out_r18 );

r19: reg

PORT MAP ( out_s5, clk, out_r19 );

r20: reg

PORT MAP ( out_s6, clk, out_r20 );

r21: reg

PORT MAP ( out_r13, clk, out_r21 );

r22: reg

PORT MAP ( out_r14, clk, out_r22 );

r23: reg

PORT MAP ( out_r15, clk, out_r23 );

r24: reg

PORT MAP ( out_r16, clk, out_r24 );

--Input to AddDiv and Difference for stage 3

a7: adddiv

PORT MAP ( out_r17, out_r18, clk, out_a7 );

s7: difference

PORT MAP ( out_r17, out_r18, clk, out_s7 );

--Input to Register 4

r25: reg

PORT MAP ( out_a7, clk, out1 );

r26: reg

PORT MAP ( out_s7, clk, out2 );

r27: reg

PORT MAP ( out_r19, clk, out3 );

r28: reg

PORT MAP ( out_r20, clk, out4 );

r29: reg

PORT MAP ( out_r21, clk, out5 );

r30: reg

PORT MAP ( out_r22, clk, out6 );

r31: reg

PORT MAP ( out_r23, clk, out7 );

r32: reg

PORT MAP ( out_r24, clk, out8 );

END haar;

Where's I'm wrong? Many thanks