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Altera_Forum
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14 years ago

testbench integer type

Dear all, Below is my testbench code that i simulate in ModelSim. --------------------------------------------------------------------- library IEEE; use IEEE.Std_logic_1164.all; use IE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I replace the integer value from "3" to 3 and "12" to 12 and its okay.

But, know i has another error:

Error (10533): VHDL Wait Statement error at reg_tb.vhd(37): Wait Statement must contain condition clause with UNTIL keyword

Most of the testbench code that I has study uses Wait statement without UNTIL keyword..I'm confuse know..Anyone help me please.

Many thanks