testbench integer type

Dear Tricky,

I has instantiate the haar.vhd file and also compile all others file in to library.

But, when I run it, the input is correct but no output is obtained. I don't know why. Below is my haar testbench code:

---------------------------------------------------------------------------

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

entity haar_tb is

end;

architecture bench of haar_tb is

-------------Component Declarations---------------

component haar

PORT (

clock : IN bit;

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

in4 : IN integer RANGE -127 TO 127;

in5 : IN integer RANGE -127 TO 127;

in6 : IN integer RANGE -127 TO 127;

in7 : IN integer RANGE -127 TO 127;

in8 : IN integer RANGE -127 TO 127;

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

out4 : OUT integer RANGE -127 TO 127;

out5 : OUT integer RANGE -127 TO 127;

out6 : OUT integer RANGE -127 TO 127;

out7 : OUT integer RANGE -127 TO 127;

out8 : OUT integer RANGE -127 TO 127

);

end component;

--------------Signal Declarations-----------------

signal clock: bit;

signal in1: integer RANGE -127 TO 127;

signal in2: integer RANGE -127 TO 127;

signal in3: integer RANGE -127 TO 127;

signal in4: integer RANGE -127 TO 127;

signal in5: integer RANGE -127 TO 127;

signal in6: integer RANGE -127 TO 127;

signal in7: integer RANGE -127 TO 127;

signal in8: integer RANGE -127 TO 127;

signal out1: integer RANGE -127 TO 127;

signal out2: integer RANGE -127 TO 127;

signal out3: integer RANGE -127 TO 127;

signal out4: integer RANGE -127 TO 127;

signal out5: integer RANGE -127 TO 127;

signal out6: integer RANGE -127 TO 127;

signal out7: integer RANGE -127 TO 127;

signal out8: integer RANGE -127 TO 127 ;

begin

---------------Component Instantiation--------------

uut: haar

port map ( clock => clock,

in1 => in1,

in2 => in2,

in3 => in3,

in4 => in4,

in5 => in5,

in6 => in6,

in7 => in7,

in8 => in8,

out1 => out1,

out2 => out2,

out3 => out3,

out4 => out4,

out5 => out5,

out6 => out6,

out7 => out7,

out8 => out8 );

stimulus: process

begin

---------------------First Test------------------

in1 <= 18;

in2 <= 5;

in3 <= 1;

in4 <= 9;

in5 <= 13;

in6 <= 6;

in7 <= 2;

in8 <= 3;

wait for 50ns;

---------------------Second Test------------------

in1 <= 10;

in2 <= 2;

in3 <= 3;

in4 <= 4;

in5 <= 15;

in6 <= 7;

in7 <= 13;

in8 <= 8;

wait for 50ns;

---------------------Third Test--------------------

in1 <= 1;

in2 <= 3;

in3 <= 11;

in4 <= 8;

in5 <= 15;

in6 <= 4;

in7 <= 6;

in8 <= 13;

wait for 50ns;

wait;

end process;

end;

Can you tell me, what I'm missing...Many thanks