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Altera_Forum's avatar
Altera_Forum
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15 years ago

testbench integer type

Dear all, Below is my testbench code that i simulate in ModelSim. --------------------------------------------------------------------- library IEEE; use IEEE.Std_logic_1164.all; use IE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear Daixiwen,

I already fix the error. I run simulate the testbench code in ModelSim and its okay.

I has one question, how to make a testbench when we have several subcode.

For example, I has four vhd file:

(1)reg.vhd (2)adddiv.vhd (3)difference.vhd (4)haar.vhd

where haar.vhd is the main file of the program.

I want to make testbench for the main file.

Many thanks