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Altera_Forum's avatar
Altera_Forum
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13 years ago

testbench and signals

as i'm new on vhdl i was wondering is there any possible way to include the signals inside the architecture in the testbench .. i built a structural design and the only output that really matters was all the signals and i want to include them in my testbench but i don't know how do i need to define them in the entity or there is another way ..

thnx very much :)

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    i'm sorry .. i'm really new to this .. i didn't understand your example i'm using active hdl 8.2 .. do i need to install another program ? is there another way that i can use in the program i'm working on ?

    thnx alot
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    do i need to install another program ?

    --- Quote End ---

    You can install Modelsim if you want to run the code I provided using the scripts I provided.

    However, in your case, just look at the testbench source code.

    --- Quote Start ---

    is there another way that i can use in the program i'm working on ?

    --- Quote End ---

    Sure. The example is written in VHDL. Just use whatever commands Active HDL uses to build the source, and then you can run the testbench.

    Cheers,

    Dave