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Altera_Forum
Honored Contributor
Honored Contributortestbench and signals
as i'm new on vhdl i was wondering is there any possible way to include the signals inside the architecture in the testbench .. i built a structural design and the only output that really matters was...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- do i need to install another program ? --- Quote End --- You can install Modelsim if you want to run the code I provided using the scripts I provided. However, in your case, just look at the testbench source code. --- Quote Start --- is there another way that i can use in the program i'm working on ? --- Quote End --- Sure. The example is written in VHDL. Just use whatever commands Active HDL uses to build the source, and then you can run the testbench. Cheers, Dave
