Forum Discussion

Honored Contributor

14 years ago

testbench and signals

as i'm new on vhdl i was wondering is there any possible way to include the signals inside the architecture in the testbench .. i built a structural design and the only output that really matters was...

Altera_Forum

Honored Contributor

14 years ago

There's a Modelsim example in VHDL in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

It shows you how to write a top-level testbench.

Cheers,

Dave

Forum Discussion

testbench and signals

Recent Discussions

Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B

Check COD for EP4CE10F17C8N

Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY

Cyclone IV GX Invalid JTAG ID Code - EPCS32

Functional fail and suspect relate to the component