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Altera_Forum's avatar
Altera_Forum
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14 years ago

testbench and signals

as i'm new on vhdl i was wondering is there any possible way to include the signals inside the architecture in the testbench .. i built a structural design and the only output that really matters was...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

i'm sorry .. i'm really new to this .. i didn't understand your example i'm using active hdl 8.2 .. do i need to install another program ? is there another way that i can use in the program i'm working on ?

thnx alot