Honored ContributorWhat is the difference between system verilog and verilog.
If you try and compile a verilog file with this inside of it for example: module hello; initial $display("Hello world"); endmodule the compiler complains that it is a system verilog file. If I were to use that code would I have to create a system verilog file within my design? can you have a verilog file and a system veriog file in the same design? Thanks
Honored ContributorThe HDL language formerly known as Verilog is now part of the SystemVerilog standard.
SystemVerilog is a much improved language, having borrowed some of the good stuff from VHDL, and adding more complete/complex assertion/verification features. Quartus and Modelsim have been happy with the code I've thrown at them so far. If you call all of your Verilog code SystemVerilog, and perhaps update always statements to use the stricter (the compiler can do better checking) always_ff, always_comb, etc. I don't think you'll have any problems. Cheers, DaveHonored ContributorI don't understand what the compiler was complaining about.
Modelsim treats any file with a *.v as Verilog (conforming to the last IEEE Verilog standard 1364-2005) and any file with *.sv as SystemVerilog. The file extensions of those included with `include are ignored - the parser does not switch modes when `including a file. SystemVerilog is supposed to be 100% backward compatible with Verilog. There is one notable exception: new keywords. For example, SystemVerilog added the keywords bit and logic. If your Verilog design used those keywords as identifiers, you would get a compiler error. There are now `begin_keywords/`end_keywords to deal with that in new revisions of SystemVerilog, but obviously you can't use those in Verilog.
