system verilog vs verilog

I don't understand what the compiler was complaining about.

Modelsim treats any file with a *.v as Verilog (conforming to the last IEEE Verilog standard 1364-2005) and any file with *.sv as SystemVerilog. The file extensions of those included with `include are ignored - the parser does not switch modes when `including a file.

SystemVerilog is supposed to be 100% backward compatible with Verilog. There is one notable exception: new keywords.

For example, SystemVerilog added the keywords bit and logic. If your Verilog design used those keywords as identifiers, you would get a compiler error. There are now `begin_keywords/`end_keywords to deal with that in new revisions of SystemVerilog, but obviously you can't use those in Verilog.