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Altera_Forum's avatar
Altera_Forum
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14 years ago

system verilog vs verilog

What is the difference between system verilog and verilog. If you try and compile a verilog file with this inside of it for example: module hello; initial $display("Hello world"); endm...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The HDL language formerly known as Verilog is now part of the SystemVerilog standard.

SystemVerilog is a much improved language, having borrowed some of the good stuff from VHDL, and adding more complete/complex assertion/verification features.

Quartus and Modelsim have been happy with the code I've thrown at them so far. If you call all of your Verilog code SystemVerilog, and perhaps update always statements to use the stricter (the compiler can do better checking) always_ff, always_comb, etc. I don't think you'll have any problems.

Cheers,

Dave