Synthesis with input pin mode constrain

If you need the logic to actually change based on the input, then you don't want to tie it off, as you need the logic.

If the user knows beforehand which mode they will use, you would want two different configuration images, one that's high and one that's low, and be sure to give the correct one to the customer. As for that pin, if it doesn't do anything in the design, then don't put it in, and if the user's driving a device pin that doesn't do anything, be sure to assign that pin as a reserved input.

(You could also go more exotic, like having both images stored, and the user determines which image to use. They could drive another device that determines the config image, like a MAX device, or just have the device configure from image 1, and that image checks the pin status, and if it's in the wrong state it issues a reconfiguration from image 2...)

--- Quote Start ---

Hi,

I am having an input to my module, which decides the mode of operation of the system.

But, the user using my IP knows that, in what mode it is going to operate so, he can permanently tie this input to HIGH or LOW based his mode requirements.

The logic required for one mode is different to another mode. Is there any option in synthesising, where i can save the hardware when working in a particular mode of my IP. I mean, can i say that the input mode pin will be always HIGH and synthesise.

Plz help me to know about this.

regards,

freak

--- Quote End ---

Hi freak,

is the input really necessary, means is there a request that you can change the operation mode running in the application ?

--- Quote Start ---

Hi freak,

is the input really necessary, means is there a request that you can change the operation mode running in the application ?

--- Quote End ---

In verilog you can use `ifdef for controlling the synthesis. I have made a small example:

module if_def_test ( clk , in , out);

input clk;

input in;

output out;

reg reg_int1, reg_int2, reg_int3;

`ifdef synth assign out = reg_int1;

`else assign out = reg_int3;

`endif

always @(posedge clk) begin

reg_int1 <= in;

reg_int2 <= in;

reg_int3 <= reg_int2;

end

endmodule

In the example the length of the register chain is controlled by setting the macro "synth".

"synth" is name of the macro, of coarse you can choose a different one. You can set the macro to "1":

Assignment -> Settings -> Analysis & Synthesis Settings -> HDL Verilog Input -> Verilog HDL Macro

Name : synth

Value : 1

Doing so only reg_int1 will be implemented. Try it and have fun.

If you tie the input to the logic then the synthesis tool should strip out any unused logic.

What language are you using?

If you're using VHDL then you could use two different architectures - just let the user compile the one they want.

You could also use a generic rather than an input port and use "if condition generate" around a block of code to incorporate one block or the other.