Synthesis with input pin mode constrain

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Hi freak,

is the input really necessary, means is there a request that you can change the operation mode running in the application ?

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In verilog you can use `ifdef for controlling the synthesis. I have made a small example:

module if_def_test ( clk , in , out);

input clk;

input in;

output out;

reg reg_int1, reg_int2, reg_int3;

`ifdef synth assign out = reg_int1;

`else assign out = reg_int3;

`endif

always @(posedge clk) begin

reg_int1 <= in;

reg_int2 <= in;

reg_int3 <= reg_int2;

end

endmodule

In the example the length of the register chain is controlled by setting the macro "synth".

"synth" is name of the macro, of coarse you can choose a different one. You can set the macro to "1":

Assignment -> Settings -> Analysis & Synthesis Settings -> HDL Verilog Input -> Verilog HDL Macro

Name : synth

Value : 1

Doing so only reg_int1 will be implemented. Try it and have fun.