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Altera_Forum
Honored Contributor
Honored ContributorSynthesis with input pin mode constrain
Hi, I am having an input to my module, which decides the mode of operation of the system. But, the user using my IP knows that, in what mode it is going to operate so, he can permanently ti...
Altera_ForumHonored Contributor
Honored ContributorIf you tie the input to the logic then the synthesis tool should strip out any unused logic.
What language are you using? If you're using VHDL then you could use two different architectures - just let the user compile the one they want. You could also use a generic rather than an input port and use "if condition generate" around a block of code to incorporate one block or the other.
