Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Synthesis timing issues

Hi,

Whenever the timing requirements are so high, it often happens that the removal of logic further decreases the fmax. For example in a project I need 400Mhz to achieve and somehow fmax just closed to 403Mhz but when I change my design by removing some logic i assumed that timing should get better. The results become more worst and fmax jumped to 386Mhz

Any idea why this happens and what is recommended?

Thanks

Ali Umair

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Go to tools -> Design Space Explorer and run a seed sweep at night on one(or both) versions. Look at the results.csv and find the setup report for your clock domain. (I look at every third column of results, which is the normal slow timing model). You'll see a spread across seeds. So your design that runs at 403MHz will really have some spread of results. Most likely 386MHz is within that range(and vice versa), so the 386MHz is not worse, just a different value in the range that can occur with different seeds.

    You could look at the following for info about the fitter and interpreting seeds:

    http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    By removing logic, you may have created latches, which often lower fmax

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    @jderrick

    No this is not the case.... I again checked synthesis warnings and there is such kind of thing. I simply removed the logic as those signals are available from other module but this should not impact any thing as I simply adds two ports in compensation. All the ports except clock and reset are virtual ports
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Its a very normal thing. Even the removal of a wire will make the results differ from what you were getting.

    like RYSC said run a seed sweep on both the versions and you will see some paths failing even with the version with which you were hitting 403.

    Each an every change you make to the RTL makes the tool to run totally in a different way. Sometimes even addition of logic can give you better results (if the logic is just one level of addition) as it can hit the best seed.

    Just check the variation with the two versions and you will have your answer.

    GOOD LUCK :)