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Altera_Forum's avatar
Altera_Forum
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13 years ago

Synthesis timing issues

Hi, Whenever the timing requirements are so high, it often happens that the removal of logic further decreases the fmax. For example in a project I need 400Mhz to achieve and somehow fmax just ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Its a very normal thing. Even the removal of a wire will make the results differ from what you were getting.

like RYSC said run a seed sweep on both the versions and you will see some paths failing even with the version with which you were hitting 403.

Each an every change you make to the RTL makes the tool to run totally in a different way. Sometimes even addition of logic can give you better results (if the logic is just one level of addition) as it can hit the best seed.

Just check the variation with the two versions and you will have your answer.

GOOD LUCK :)