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Altera_Forum
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13 years ago

Synthesis timing issues

Hi, Whenever the timing requirements are so high, it often happens that the removal of logic further decreases the fmax. For example in a project I need 400Mhz to achieve and somehow fmax just ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

@jderrick

No this is not the case.... I again checked synthesis warnings and there is such kind of thing. I simply removed the logic as those signals are available from other module but this should not impact any thing as I simply adds two ports in compensation. All the ports except clock and reset are virtual ports