Synthesis timing issues

Go to tools -> Design Space Explorer and run a seed sweep at night on one(or both) versions. Look at the results.csv and find the setup report for your clock domain. (I look at every third column of results, which is the normal slow timing model). You'll see a spread across seeds. So your design that runs at 403MHz will really have some spread of results. Most likely 386MHz is within that range(and vice versa), so the 386MHz is not worse, just a different value in the range that can occur with different seeds.