Honored ContributorHello,
I got problem that my EPCS cannot reconfig STRATIXIII. My VCCIO of I/O bank 3 is powered by 1.5V and the configuration signals used require 2.5-V signaling. Should I connect VCCSEL to VCCPD in order to enable the 1.5V input buffers for configuration.? STRATIX II have VCCSEL pin, but I cannot find on STRATIX III. Thanks
Honored ContributorI hear some confusion from your post, I think, you may want to read the Startix III hardware manual more thoroughly. The basic point with AS configuration scheme is to provide a correct VCCPGM supply, with Altera EPCS devices, it has to be 3.3V. The bank containing the DATA0 pin should have at least a VCCIO of 2.5V, otherwise some means of level translation, e.g. a resistive divider would be necessary (not an Altera suggested solution, but should work anyway).
Honored ContributorThanks. I am clear on this circuitry now. The bank for that DATA0 happened to be 1.5V; therefore, I have to use resistor divider.
Are 6K on EPCS side and 5K from data0 to GND fine?Honored ContributorFVM,
I connected one end of 6K to EPCS side, the other end to STRATIXIII and to 5K to GND. However, the programmer complained that it cannot recognize the EPCS ID. Any suggestion to connect these voltage divider? ThanksHonored ContributorThe divider must have a lower impedance to work at 40 MHz FPGA clock, e.g. 1k each resistor. I didn't test the solution with a EPCS device, it's working correct with other logic devices.
USB Blaster access uses 6 MHz at maximum and should work however, so there's apparently a different problem. How do you connect the programmer? I suggest indirect JTAG programming.Honored ContributorI use indirect JTAG programming. Attached is the schematic how I connected the JTAG
1) Since the VCCIO for bank contained data0 (Bank1C) is connected to 1.5V; therefor, I follow your instruction to add resistor divider. How do I connect these resistors? 2) From schematic, do I connect JTAG pin 4 correctly? Should I change these 2.5V to 3.3V? 3) Should I change 2.5V_VCCPGM to 3.3V? ThanksHonored ContributorAccording to the Stratix III handbook, VCCPGM should be connected to 3.3V. I don't know, if the AS device is possibly working with 2.5V as well.
My suggestion for a voltage divider is one 1k resistor from EPCS.DATA to FPGA.DATA0 and one from FPGA.DATA0 to GND. But I didn't try it, in case of difficulties you should check for valid H and L voltage levels when accessing the EPCS device trough JTAG indirect programming. Are you using the default Stratix III SFL design or SFL embedded to your design?Honored ContributorI tried 1K resistors as suggested, but the FPGA cannot reconfig.
I included the SFL circuitry in the FPGA; therefore, the programmer could recognize the EPCS device ID, erase the ASP config, and programming successful (from programmer messages).Honored ContributorYou should try the default SFL design, to verify, that your not facing any kind of configuration problem in your design. You also should check, if all EPCS pins (nCS, DCLK, ASDI) are actually toggled when acessing the device by the programmer, also if DATA is activated at the EPCS device. If all these points check O.K., ask Altera support, what's their suggestion to connect DATA0 in a 1.5V bank.
