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Honored Contributor
Honored ContributorStratixIII EPCS problem VCCSEL?
Hello, I got problem that my EPCS cannot reconfig STRATIXIII. My VCCIO of I/O bank 3 is powered by 1.5V and the configuration signals used require 2.5-V signaling. Should I connec...
Altera_ForumHonored Contributor
Honored ContributorThe divider must have a lower impedance to work at 40 MHz FPGA clock, e.g. 1k each resistor. I didn't test the solution with a EPCS device, it's working correct with other logic devices.
USB Blaster access uses 6 MHz at maximum and should work however, so there's apparently a different problem. How do you connect the programmer? I suggest indirect JTAG programming.
