Occasional ContributorI have two image in QSPI flash,both have PCIe funtion, It is hoped that the PCIe will not be hung up during image switching，There is some example design or user guide for provide reference.
By the way,which IP core can provide multi boot function for S10?
Thanks!!! have a nice day.
Regular ContributorHi Guo,
In your design, are you using PCIe as the interface to program the FPGA? If not, then you will just need to generate the bitstream as usual with PCIe design in Quartus design.
To perform multiboot function, it depends on the configuration scheme that you are using. It can be Active Serial or AVST. For active serial, you will need to have "mailbox IP" or "serial flash mailbox ip". For AVST, you will need "PFL II IP" and a host (it can be processor, CPLD or MAX 10).
For more information, you may refer to link below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/archives/ug-s10-config-17-1.pdf
Thank You.
Occasional ContributorWhen I switch between two iamges that contain PCIE, won't it hang because of this?
Regular ContributorSo you are using PCIe to transfer the image file? Is it so?
Occasional ContributorI'm thinking that there may be some gap time between two images switch to load the code, so that the host fail to recognize the PCIe during this time and hangs up
Regular ContributorAssuming you are using active serial configuration scheme which you will program the flash first with PCIe. The image will not be programmed into FPGA from flash unless you have rebooted. Thus, it wouldnt affect it.
New ContributorI don't use PCIe to transfer the image file. just both image in the flash have PCIe function, when i use "mailbox ip" to update image , I just think there is some gap when switch to image . so that the host fail to recognize the PCIe during this time and hangs up.
image1 has PCIe function, and image2 has same PCIe function. the host driver will be failed when change two image using "mailbox ip"?
Thanks!!! have fun.
Regular ContributorHi De-xin,
When you said about host, is it the processor which is connected to FPGA via PCIe? If it so, it depends. However, if the PCIe address that is recognised by the processor is still the same, i am sure that the host will not fail to recognize the PCIe. Is all depend on host side.
Thank You.
New ContributorSorry for my expressiveness, thank you for solving my confusion, thank you
