Occasional Contributor
Regular ContributorHi Guo,
In your design, are you using PCIe as the interface to program the FPGA? If not, then you will just need to generate the bitstream as usual with PCIe design in Quartus design.
To perform multiboot function, it depends on the configuration scheme that you are using. It can be Active Serial or AVST. For active serial, you will need to have "mailbox IP" or "serial flash mailbox ip". For AVST, you will need "PFL II IP" and a host (it can be processor, CPLD or MAX 10).
For more information, you may refer to link below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/archives/ug-s10-config-17-1.pdf
Thank You.
Occasional ContributorWhen I switch between two iamges that contain PCIE, won't it hang because of this?
